The present invention generally relates to mass storage devices adapted for use with personal computers, servers, or other host systems. Specifically, the invention relates to a solid state drive (SSD) containing NAND flash-based memory components that are dynamically reconfigurable to operate in different modes, one being relatively faster and another effectively multiplying the capacity of the drive.
NAND flash memory has become the storage medium of choice for solid state drives used in personal computers and servers. Flash memory, regardless of whether it is NAND or NOR technology that is implemented, uses floating gate transistors (FGT) to store data wherein each FGT constitutes a cell as the smallest physical unit to hold a bit. NAND flash cells are organized in what are commonly referred to as pages, which in turn are organized in predetermined sections of the component referred to as memory blocks (or sectors). Each cell of a NAND flash memory component has a top or control gate (CG) and a floating gate (FG), the latter being sandwiched between the control gate and the channel of the cell. The floating gate is separated from the control gate by an oxide layer and from the channel by another oxide layer, referred to as the tunnel oxide. Data are stored in a NAND flash cell in the form of a charge on the floating gate which, in turn, defines the channel properties of the NAND flash cell by either augmenting or opposing the charge of the control gate. The process of programming (writing 0's to) a NAND cell requires applying a programming voltage to the control gate, which causes the injection of electrons into the floating gate by quantum mechanical tunneling. The process of erasing (writing 1's to) a NAND cell requires removing the programming charge from the floating gate by applying an erase voltage to the device substrate, which pulls electrons from the floating gate. Data are stored, retrieved and erased on a block-by-block basis. In view of the above, the operational principle of a NAND flash memory component is that the floating gate, which is interposed between the control gate and channel, is charged to have an additional charge that supplements or counteracts a control voltage applied to the control gate. At a certain threshold the control voltage will switch the transistor “On” or “Off.” Accordingly, programming or writing (and erasing) of a NAND cell entails charging of its floating gate, whereas reading of data stored in a NAND cell entails sensing the threshold of the control voltage at which the transistor switches.
One of the key events that has enabled NAND flash to become competitive for mass storage devices or solid state drives was its evolution to be able to store two bits per cell, which entails sensing of the switching threshold to unambiguously identify four different voltage levels. This particular “generation” of flash memory is called multi-level cell (MLC) flash memory in order to distinguish it from the older single-level cell (SLC) flash memory which could only store a single bit per cell. The relation between the number of bits stored in each cell and the voltage levels (lv) that need to be distinguishable is the simple binary function n(lv)=2n(bit).
For example a single level cell storing only one bit will require 21 levels, above and below a trip-voltage threshold to be uniquely identifiable, whereas a multi-level cell with two bits per cell will require separation of 22 (4) levels. In the upcoming migration to triple level cell (TLC) technology, 23 (8) different levels need to be distinguishable.
Most current flash cells operate at a voltage sensing range of less than 2V, depending on the manufacturer and the process. Each bit value has a quasi-Gaussian distribution across all cells used with reference points as the threshold between digital 0 and 1 values. As cells age and more electrons become trapped in the oxide layer separating the floating gate from the substrate, these trapped charges will cause the distribution of “effective” programming charges to shift. In other words, the transistor does not know where the charges are and, therefore, charges trapped in the oxide layer will have the same effect as charges programmed into the floating gate. The result is that trapped charges in the oxide layer are additive to the floating gate charge. This results in incremental difficulties to maintain the correct charges for the desired bit values between the reference points since additive action of the oxide trapping can lead to over-programming or else failure to properly erase any given cell within a block.
Programming of cells is done through incremental step pulse programming (ISPP), wherein the desired value is correlated with a look-up table that takes into account any charges that are already present. The latter only applies to MLC or TLC flash memory since SLC memory programming will always start at a fully erased state of the cell.
MLC flash memory deviates from SLC flash memory in its logical organization of the data structure. In short, instead of programming the two bits in a single pass of a programming voltage applied to the control gate, the two bits are programmed separately. For example, an MLC cell may be programmed from a starting point of 11 to a 10 level by doing a first pass charging of the floating gate. The upper bit is then programmed using a second pass charging of the floating gate.
In theory, the two bits stored in any NAND cell could be part of the same page. However, for practical reasons, the upper and lower bits of each cell are assigned to separate logical pages. Moreover, in order to simplify programming of upper and lower pages, a generally accepted strategy is to program a number of pages for the lower bit first and then loop back to the same physical bitlines in order to program the upper pages. This second pass also requires the controller to know about the programming state of the target cell in order to select the correct programming pulse.
From the above, it should be understood that SLC NAND flash memory is more robust and easier to program in comparison to MLC and TLC NAND flash memory. Moreover, because of using only a single reference point between the two charge states associated with a digital 0 or 1, SLC flash memory also requires much less precision for the programming. A different way of looking at this is that SLC flash memory is much faster and also much more fault tolerant than MLC flash memory. By extension, this also means that SLC flash memory has a much higher endurance, typically in the range of 50 k to 100 k write cycles as opposed to MLC flash memory with 3 k to 5 k write cycles and TLC flash memory with an estimated 300 to 500 write cycles before reaching the endurance limitation at which cells can no longer be reliably programmed.
The advantages of SLC and MLC flash memory have been combined in hybrid drives using both technologies. In this case, SLC flash memory is used as a first tier or cache and MLC flash memory is used as large capacity storage, thereby taking advantage of the best of both worlds. In any such device, though, the capacities of the SLC and MLC flash memory spaces are fixed, which inadvertently leads to one of the two wearing out faster than the other.